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Please use this identifier to cite or link to this item: http://hdl.handle.net/1860/1065

Title: Delay insertion method in clock skew scheduling
Authors: Taskin, Baris
Keywords: Delay padding;digital synchronous very large scale integration (VLSI) circuit timing;nonzero clock skew scheduling;reconvergent paths;Integrated circuits
Issue Date: Apr-2006
Publisher: IEEE
Citation: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 4, APRIL 2006
Abstract: This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. It is shown that reconvergent paths limit the improvement of circuit performance achievable through clock skew scheduling. A delay insertion method is proposed such that the optimal clock period achievable through clock skew scheduling is improved by mitigating the limitations caused by reconvergent paths. Experimental results demonstrate that reconvergent paths are limiting for 34% (41% for level sensitive) of the selected suite of ISCAS’89 benchmark circuits. Through the application of clock skew scheduling with delay insertion, an average improvement of 10% shorter clock periods (9% for level sensitive) is observed for ISCAS’89 benchmark circuits compared to the results of conventional clock skew scheduling.
URI: http://hdl.handle.net/1860/1065
Appears in Collections:Faculty Research and Publications (ECE)

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