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Please use this identifier to cite or link to this item: http://hdl.handle.net/1860/1770

Title: The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration
Authors: Balog, Michael
Keywords: Electric engineering;Field programmable gate arrays;Gate array circuits
Issue Date: 4-Sep-2007
Abstract: Over the past few years FPGA hardware has become a logical choice for implementing cutting-edge signal processing applications. While there have been advances in FPGA technology, the common process of creating specialized hardware implementations for them is a manual one involving extensive design exploration. Design exploration is a process that requires a designer to look for designs that ¯t a set of performance characteristics such as size, throughput, or power depending on the application and it can be the most time consuming step when creating FPGA hardware. This process is a nontrivial task that requires extensive background knowledge of both FPGA hardware and the application being implemented. While advances have been made in automating the process of design, there is still a gap between the application writers and hardware engineers that can be filled. This thesis presents a novel approach for automating the generation of hardware design search spaces that contain a comprehensive set of ways to implement signal processing algorithms with FPGAs. To accomplish this we generate a set of equivalent mathematical representations for an input equation via a novel declarative programming language that avoids a number of di±culties associated with the imperative languages used by previous approaches. We show that this equation space is bounded in terms of bracketing and ordering of mathematical operations, and that by changing the way an equation is written we can generate unique hardware instantiations (designs). The generated instantiations are mapped to heterogeneous computing architectures and written in a structural hardware descriptive language style to ensure that the intended instantiation will behave as predicted in hardware. A software system was created based on this approach that generates an equation space for varying numbers of summed multiplications and converts each representation into a comprehensive hardware design search space that can be analyzed for performance characteristics such as size, throughput, latency, and power.
URI: http://hdl.handle.net/1860/1770
Appears in Collections:Drexel Theses and Dissertations

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